A METHOD OF SYNTHESIZING IRREDUNDANT CIRCUITS, ADMITTING SMALL SINGLE FAULT DIAGNOSTIC TEST SETS AT STUCK-AT FAULTS AT OUTPUTS OF GATES

Romanov Dmitriy Sergeevich. Candidate of physical and mathematical sciences, associate professor, sub-department of mathematical cybernetics, Lomonosov Moscow State University (1 Leninskie gory street, Moscow, Russia), romanov@cs.msu.ru
Romanova Elena Yur'evna, Candidate of pedagogical sciences, associate professor, sub-department of applied mathematics, Russian State Social University (building 1, 4 Wilgelma Pika street, Moscow, Russia). klenar2001@mail.ru

519.718

10.21685/2072-3040-2016-2-8

Background. Testing of combinational circuits is an important theoretical problem with applications in testing and verification of VLSI. The aim of this work is to demonstrate that for an arbitrary Boolean function it is possible to construct a circuit realizing this function and allowing small single fault diagnosing test set (at stuck-at faults at outputs of gates).
Materials and methods. Circuit design methods based on Zhegalkin polinomials (canonical Reed-Muller polinomial forms) were used.
Results. It is established that for an arbitrary Boolean function f depending on n variables there exists an irredundant combinational circuit (in the basis {x&y, x+y, 1}) realizing f and admitting a single fault diagnosing test set (at stuck-at faults at outputs of gates) with constant cardinality.

combinational circuit, fault diagnostic test set, stuck-at fault at output of gate, Shannon function, easily testable circuit.

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